Integrated circuit devices such as synchronous dynamic random access memory (SDRAM) devices typically include internal clock generating circuits that generate internal clock signals in-sync with an externally applied clock signal. In an SDRAM, many of the internally generated signals are generated in response to the internal clock signal. For example, the internal clock signal may control the timing of circuits which output data from the SDRAM and receive data into the SDRAM.
Conventional SDRAMs typically synchronize an internal clock signal to an external clock signal using a phase-locked loop (PLL) or a delay-locked loop (DLL). Both the PLL and DLL utilize feedback to insure that exact synchronization is achieved.
Techniques have also been developed for reducing the power consumed by SDRAMs. Such techniques often include the use of a power-down or standby mode. During these modes, certain circuits within the SDRAM are made inactive and consume less power. However, when switching from a standby mode to an active mode, some time is typically required to stabilize the PLL or DLL circuits and the duration of this time is typically influenced greatly by the operating speed of the SDRAM. Moreover, because PLL and DLL circuits typically utilize feedback, several hundred to several thousand clock cycles may be required before such circuits become stabilized when reentering an active mode.
Synchronous delay inversion technologies have been employed to reduce the time required to achieve synchronous operation upon resumption of an active mode. An example of this technology is disclosed in an article by Saeki et al., entitled "A 2.5 ns Clock Access 250 MHz 256 Mb SDRAM with a Synchronous Mirror Delay", ISSCC96, Paper SP 23.4, pp. 374-375 (1996), and in U.S. Pat. No. 5,742,194 to Saeki, entitled "Internal Clock Generator for a Synchronous Dynamic RAM". Unfortunately, this synchronous delay inversion technology may require the use of a digital circuit. In particular, the delay time corresponding to the electrostatic capacitance of the SDRAM and characteristics of the input/output multiplexer is digitized and this digitization may result in a quantization error. In addition, a delay error can be generated in the output clock signals generated using the delay inverter having an quantization error. The maximum time of the error corresponds to the time of one step during digitization. The step time is the delay time of the inverter. Since the delay time of an inverter may exceed 100 picoseconds, the error associated with the output clock can be greater than 100 ps. Thus, notwithstanding the conventional use of PLLs or DLLs to obtain synchronization, there still exists a need for improved circuits for generating internal clock signals with improved synchronization.